TSMC reports Thursday, and it reads the whole AI cycle

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This Thursday, July 16, 2026, Taiwan Semiconductor Manufacturing ($TSM) reports its second-quarter results. I circle this date every three months, because TSMC is about as close as we get to a single read, on the manufacturing side, of whether the AI buildout keeps speeding up or starts to level off. The large majority of leading-edge AI accelerators, whatever logo ends up on the box, get manufactured inside its fabs. When NVIDIA, AMD, Apple, and the big cloud players want the most advanced silicon, this is where they line up. So one earnings call doubles as a demand check on the entire compute stack at once.

The mix makes the point. In the first quarter of 2026, high-performance computing, the segment that includes AI and data-center chips, made up 61% of TSMC's revenue, according to the company, the first time it crossed 60% and well ahead of smartphones at 26%. Gross margin ran about 66% that quarter, high even by TSMC's own historical standards, and unusually high for a company that actually builds physical things. When a manufacturer this central talks about next year, it is really telling you how much compute the world is planning to build.

I go into every TSMC quarter watching the same four signals: the packaging bottleneck, gross margin and pricing, the 2nm ramp, and the full-year guide. Together they tell you far more about where the cycle is heading.

TSMC's advanced packaging process, called CoWoS, is the step that binds a big AI processor to its stacks of high-bandwidth memory on a single module. Picture assembling several separate chips onto one tray so they behave like one much larger chip. For roughly two years, the binding constraint on the most advanced accelerators has been this packaging step rather than the chipmaking itself, which makes it the narrowest point on the entire assembly line.

Capacity here has grown several times over in about two years. Industry reporting points to a target somewhere around 125,000 to 130,000 of these wafer-units per month by the end of 2026, a multi-fold jump from 2023 levels, and management has portrayed the capacity as effectively fully committed and tight through 2026. What I want Thursday is simple: is that expansion timeline still holding, and does management still describe packaging as sold out rather than "balanced" or "healthy." As long as packaging keeps filling as fast as it comes online, today's AI orders are still constrained by supply, which is the clearest sign the demand is real rather than hoped for.

Gross margin is just how much of each sales dollar survives after the cost of making the chip. TSMC guided the June quarter to somewhere in the range of 65.5% to 67.5%, and it printed around 66% the quarter before. Two forces pull on that number in opposite directions.

Pricing power pulls it up. Customer checks and press reporting point to price increases in the 5% to 10% range on TSMC's most advanced processes, and so far customers appear to be paying. New-fab costs pull it down: spinning up the brand-new 2nm line and building fabs in Arizona, Japan, and Germany carries several points of potential margin drag over the ramp while those plants fill. One more swing factor sits outside the business entirely, since a favorable move in the Taiwan dollar lifted reported margin in recent quarters, so I try to separate real pricing power from currency. The tell I listen for is whether pricing keeps offsetting the fab drag. If margin holds in that guided band while three overseas fabs ramp at once, it says TSMC's pricing leverage over its customers remains intact.

A "node" is a chip generation. Smaller number, more advanced. TSMC's next generation, called N2 (2 nanometer), is moving toward high-volume production. Company commentary points to early production as we move through 2026 and a high-volume ramp into 2027, with 2nm-class capacity set to scale at a very steep pace over the following couple of years. This is the next leg of the story, because early N2 demand is dominated by AI accelerators and flagship phone chips that pre-book this capacity years ahead of shipping anything, so any color on the customer mix is an indirect read on who wins the next node.

On Thursday I listen for how the ramp and the yields are tracking. Yield is the share of good chips per wafer, and early yields decide how profitable a new node becomes and how confidently customers commit. Any color on 2nm pricing matters too, since it sets the ceiling on margins for years.

The most important sentence of the call won't be the quarter that already happened. On the prior call, TSMC raised its full-year 2026 revenue growth outlook to above 30% in U.S.-dollar terms, citing AI demand. The open question is whether they nudge that figure higher again or simply hold it.

A raise says the buildout is still accelerating. Holding steady says it's healthy and pacing itself. Either can be fine, but that one line tends to move the whole chip complex, because everyone downstream of TSMC reprices around what the factory expects. This is the number I'd read first.

The rest of this issue, how I'd read the print and what it means for every chip name I hold, is for paid subscribers.