Hi {{first_name | Investor}},
This week, TSMC reported Q1 2026 revenue of $35.9 billion — net profit up 58% year over year, beating estimates and setting a fresh record. They also confirmed their 2026 capital expenditures budget is tracking toward the high end of a $52–56 billion range.
On the earnings call, CEO C.C. Wei explained what's driving it. The story isn't just that AI demand is strong — it's that the nature of AI is changing. His exact words: "The shift from generative AI and the query mode to agentic AI and command and action mode is leading to another step-up in the amount of tokens being consumed." Query mode means you ask a question and get an answer. Agentic mode means AI takes actions, runs sequences, operates autonomously. Each step in that chain consumes compute. The demand curve isn't linear — it's compounding.
But here's the thing most coverage missed: TSMC isn't spending $50+ billion on chips. They're spending it on everything that makes advanced chips possible — the packaging infrastructure, the inspection equipment, the substrates, the thermal systems. The chip is the headline. The supply chain is where the capital actually lands.
In this issue, I want to map where that spending potentially goes. There are US-listed names in this supply chain worth watching — and I am watching them. But the more interesting companies, in my view, are the non-US listed names that most US-based investors have never looked at. That's what I want to focus on here, and the reasons why are worth understanding before you look at any of the companies.
Why the supply chain is where this gets interesting
TSMC doesn't build chips in isolation. Every wafer that comes out of a TSMC fab required substrates to mount on, inspection tools to verify, advanced packaging to assemble, and thermal systems to manage the heat that comes with stacking dozens of chiplets in increasingly dense configurations. The fab is the center of gravity — but the capital flows outward to every supplier that makes the fab's output possible.
The leading-edge chips TSMC fabricates are becoming harder to assemble, not just more valuable to design. When you're routing thousands of connections between chiplets inside a single package, every layer of that process — the substrate carrying the signals, the inspection tools verifying nothing failed, the packaging technology holding it all together — becomes load-bearing. A failure anywhere in that chain costs more as the chips get more complex and more expensive.
That's where the incremental profit is shifting. And TSMC's own capital commitment tells you how long the runway is.
And this isn't a one-quarter story. CFO Wendell Huang put the CapEx trajectory in stark terms on the call: TSMC's total capital spend for the past three years combined was $101 billion. This year alone they're guiding to $56 billion — already more than half of the last three-year total. His forward guidance: the next three years will be "significantly higher" than the last three. This begs the question: Is the market correctly pricing the supply chain names that sit beneath TSMC's fab expansion given the "significantly higher" spend?
Four areas worth watching — and how I'm thinking about each
Each of these areas has US-listed counterparts — Teradyne and Onto Innovation in inspection, Broadcom and Marvell in custom silicon, Vertiv and nVent in thermal. Those are real businesses and reasonable ways to get exposure to this theme. But they also carry US large-cap valuations and significant analyst coverage. The non-US names I'm focused on operate in the same supply chain with less overlap to the US mega-cap chip set, and in some cases trade at a meaningful valuation dispersion relative to their growth and capacity expansion profiles. That gap is what makes them worth the additional complexity.
The connection to TSMC's CapEx is not equal across all four areas, and I think it's worth being clear about how directly each one ties back to the thesis.
The highest-conviction segment is IC substrates. A substrate is the base layer a chip sits on — it routes electrical signals between the chip and the rest of the system, and as chips get denser and more complex, the substrate has to handle more connections in less space. Companies like Ibiden (Japan), Unimicron, and Nan Ya PCB (both Taiwan) are capacity-constrained suppliers of exactly these components. Substrate availability has been a genuine bottleneck as AI packaging density has increased, and TSMC's CapEx commitment is the kind of catalyst that justifies the capacity expansion these companies have been debating. I'm watching substrate ASPs (average selling prices), yield rates, and customer qualification progress as the signals that tell me whether the thesis is moving in the right direction.
Close behind are the advanced packaging inspection and test names — Camtek (Israel), MA-tek, and IST (both Taiwan). C.C. Wei said it plainly on the call: "Our advanced packaging capacity is very tight also." That's not analyst speculation — it's the CEO confirming the bottleneck. As packaging gets denser and more failure-sensitive, the tools that verify everything works before it touches a live AI cluster become more critical, not less. These companies sit close to the yield bottleneck — yield being the percentage of chips that come out of manufacturing without defects. When you're assembling a $30,000 AI accelerator, a bad yield rate is an expensive problem. The metrics I track here: order intake, utilization rates, and how fast advanced packaging is growing as a share of their revenue mix.
On the design side, ASIC enablers like Alchip and GUC (both Taiwan) and Socionext (Japan) aren't Broadcom substitutes — they're a different animal. An ASIC (Application-Specific Integrated Circuit) is a chip designed to do one thing extremely well, rather than a general-purpose processor that handles everything adequately. When a hyperscaler or AI lab wants their own custom chip optimized for their specific workload, they need someone to design and engineer it — that's what these firms do. The opportunity is structural: as more companies decide they want proprietary silicon rather than off-the-shelf hardware, the design services market grows with them. Revenue growth, design win momentum, and customer concentration are what I'm watching.
The fourth segment — thermal and power infrastructure, including Delta Electronics, LuxNet, and ShunSin — sits further from the core thesis. These companies benefit from AI buildout broadly, but the connection to TSMC's CapEx specifically is more indirect than substrates or inspection. Worth watching, but worth understanding the distinction before putting them in the same category as the others.
What makes this map harder to execute
I want to name the risks clearly, because they're real.
Every company in this report is listed on a non-US exchange — Taiwan or Japan primarily. That means currency exposure, different reporting standards, liquidity differences, and for Taiwan-linked names specifically, geopolitical risk that isn't theoretical. Time-zone gaps also mean overnight moves can be wider and harder to respond to. These aren't reasons to avoid the thesis — but they are reasons to size positions to reflect the additional complexity, and to weight names with stronger liquidity and clearer end-market disclosure more heavily than smaller, less transparent listings.
Non-US investing isn't harder in principle. It's just different. The names with stronger liquidity and clearer end-market disclosure deserve more weight than smaller, less transparent listings — and position sizing should reflect the full complexity, not just the thesis.
As always: I won't tell you what to buy. I'll sharpen the lens you use to look. DYOR.
Stay disciplined,
Koh