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Picking up from Thursday’s issue, the HBM4 transition is the catalyst reshaping the cost curve under the memory makers, and the structural margin sits one layer above the memory side itself: in the inspection, metrology, packaging, and test infrastructure that keeps the yield cliff manageable.

Quick recap before the basket. HBM is a stack of eight to sixteen DRAM dies layered vertically. Compounding yields at 16-layer stacks plus the move to direct copper-to-copper hybrid bonding plus the introduction of foundry logic into the base die converges into the yield cliff. The companies selling the diagnostic tools, the test equipment, and the packaging infrastructure that absorb that cliff capture stable margin regardless of which memory maker wins.

I framed two doors in Thursday's issue, the contrarian inspection door and the demand-side memory door. For the full basket, those two doors plus the advanced packaging supply chain that sits underneath both give you three layers worth understanding. Here's the framework for each before the names.

Layer one: inspection, metrology, and test

The companies here sell the tools that measure atomic flatness, scan for sub-surface voids, and electrically probe individual dies before bonding. As HBM4 raises the inspection intensity per wafer above HBM3E levels, this layer's revenue per HBM4 wafer scales whether or not memory unit volumes grow.

Two sub-tiers matter for understanding the basket. The metrology and macro-inspection tier covers the front-end and back-end optical, X-ray, and atomic-scale measurement systems. The automated test equipment tier covers the electrical probing of wafers before they ever get bonded into a stack. Both are essential for HBM4 yield management, and the companies in each tier benefit from the structural shift away from end-of-line testing toward inspection at every insertion step.

Layer two: the memory makers themselves

Three credible HBM suppliers exist globally (Micron, SK Hynix, and Samsung), and the one that climbs the HBM4 yield curve fastest tends to take share from the other two. The HBM3E demand setup has been strong across all three for the past year, but HBM4 reshuffles the deck because the yield reset hits everyone at the start of the ramp. Whichever supplier shows the best yield discipline and the cleanest power efficiency profile through early HBM4 production tends to win the disproportionate share of the hyperscaler contracts that follow.

Layer three: the advanced packaging stack

The HBM stack only matters once it's been integrated with a logic chip into a final AI accelerator package, and that integration happens through CoWoS (Chip-on-Wafer-on-Substrate) and the back-end assembly process. The companies that build the foundry-side advanced packaging, the back-end assembly capacity, and the hybrid bonding equipment that HBM4 specifically requires all sit in this layer.

The HBM4 transition raises the bar on this layer too. Hybrid bonding tools become structurally relevant for the first time, and back-end assembly throughput becomes a real constraint on how fast the cycle ramps.

All three layers have publicly traded expressions, and the basket below is how I'm covering them in my own portfolio.

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